An integrated circuit lead frame generally consists of a die paddle for mounting the integrated circuit (IC), leads that connect the integrated circuit to the package exterior, and a support structure that holds the frame together through the assembly operation. There are various configurations of lead frames currently in use in the semiconductor packaging industry including lead-on-chip (LOC) and lead-under-chip (LUC) configurations. These LOC packages have a unique mechanical configuration that, when assembled, best accommodate the needs of memory architecture.
Memory architecture is heavily influenced by the objective of providing an evenly distributed I/O channel (bus) across all the memory cells within the device. Desired characteristics driving this include lower operating voltages, which make the device more sensitive to voltage drops (spikes), higher gate densities, faster access times, and increased clock speeds (shorter paths). Thus, a large number of memory devices are typically designed with the I/O interface (aluminum bond pads) in a row bisecting the active side of the die. This centerline configuration provides minimized power, ground, and signal paths to every cell within the structure. LOC designed packages uniquely accommodate the I/O interface with a centerline bond configuration fanning out to perimeter leads.
A basic LOC package structure employs an etched or stamped lead frame that incorporates a centerline slot into a die paddle. The die paddle is connected to the leads and the frame via a tie bar that is eventually removed. During package assembly, the die is mounted against the die paddle with the active side (I/O side) down against the paddle base, leads on the opposite side. Package assemblers use a variety of die attachment methods, including tape and liquid adhesive. As the die is mounted, the I/O connections (aluminum bond pads) on the die are left exposed on the opposite side via the centerline slot. The bond pads are then electrically connected to the leads via conventional Au wire bond techniques. Once the device is wired, the structure can be overmolded or liquid encapsulated to protect the silicon and wires. The superstructure (frame and tie bars) can then be removed, if not removed already, and the devices are left singulated from the frame. The end configuration of the device can take numerous shapes based on lead frame technology used, but varieties include a small outline package (SOP), small outline integrated circuit (SOIC), plastic leaded chip carrier (PLCC) or a thin shrink small outline package (TSSOP). The lead frame technology and assembly techniques described are widely used within the industry.
Over the past five years, silicon trends have placed greater demands on the electrical, thermal, and reliability performance these LOC devices. One such trend relates to the gate densities now being achieved in the silicon itself. As device geometries decrease, the gate densities of memory devices have increased dramatically. Increased gate density translates into higher power concentration in smaller areas, which means more heat. Most LOC packages manage this heat by using a metal die pad, but the heat dissipation performance is reduced by the plastic encapsulant, a poor heat conductor, and the small surface area of the leads through which the heat is transmitted. Failure to properly manage the heat generated by the integrated circuit can result in an accelerated failure of the device circuitry.
A second trend stressing conventional LOC packaging is clock speed. The system's need for faster access times and greater bandwidth have driven memory clock speeds into the microprocessor realm of near and over 1 gigahertz. These clock speeds demand improved (lower) line inductance, power/ground networks, and shielding that plastic LOC packages cannot deliver due either to materials sets and/or lead configuration limitations. Finally, high-speed memory is permeating many high performance systems where the reliability of plastic (moisture absorbing) LOC packages comes into question.
Additionally, recent manufacturing trends have further compromised the effectiveness of traditional LOC packages. These tends involve the transition from traditional leaded integrated circuit packages to ball grid array (BGA) integrated circuit packages in a majority of high performance silicon applications. The main drivers of this trend include improved surface mountability, smaller package footprints, greater package densities, and growing assembly infrastuctures. A need has thus arisen for a new LOC substrate solution for high speed memory packaging that has the advantages of a BGA package and has enhanced thermal and electrical properties. These and other needs are satisfied by the ball grid array substrate package of the present invention.